Noise Pulse Eliminator

FSM + Verilog filter that rejects single-cycle glitches and stabilizes the measured signal.

Digital Design • HDL • FSM • Testbench

Overview

This design suppresses brief high/low spikes (≤ 1 clock) using a four-state Moore FSM implemented in Verilog, producing a clean, debounced output suitable for downstream logic. It was validated with a targeted stimulus sequence and waveform inspection.

Deliverables

FSM Design: Four states with one Moore output (glitch-filtered).
Verilog Module: Encoded states with one/two always blocks.
Testbench: Simulation covering single-cycle spikes and valid transitions.

Future Improvements

Adjustable thresholds: Parameterize window length for different noise profiles.
Async input sync: Add 2-FF synchronizers before FSM for metastability mitigation.

Code

View the Verilog implementation and simulation:

Open HDLBits Demo →

Gallery

FSM Diagram — **FSM diagram**
State flow ensuring spikes don’t toggle output.

Waveform Timing — **Timing waveform**
Single-cycle glitches suppressed; valid edges pass.

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