Noise Pulse Eliminator

by Nathan Rahbar

Deliverables

• FSM Design: Create a state diagram with four states and one Moore output.
• Verilog Module: Code the logic using one or two always blocks with appropriate state encoding.
• Testbench: Simulate using a given input sequence to verify the design.

Future Improvements

• Adjustable Noise Threshold: Enable the system to dynamically adjust filtering thresholds based on operating conditions.
• Asynchronous Input Handling: Add synchronization logic for asynchronous signal environments.

Code

You can view the full Verilog implementation and simulation on HDLBits: